Basic Computer Structure
Computer terminology; the CPU, memory and input/output blocks; the address, data and control buses; memory devices — RAM, ROM, PROM, EPROM, EEPROM and Flash — and their volatility.
Basic computer structure — summary notes
Free- A computer has four functional blocks: input, the central processing unit (CPU), memory, and output. The CPU itself contains the arithmetic and logic unit (ALU), the control unit and the registers.
- Three buses interconnect them: the ADDRESS bus (unidirectional, CPU → memory, selects a location), the DATA bus (bidirectional, carries the contents) and the CONTROL bus (read/write, clock, interrupt, reset).
- The width of the address bus fixes how much memory can be addressed — n address lines reach 2ⁿ locations. The width of the data bus fixes how many bits move at a time.
- RAM is volatile read/write working memory and loses its contents at power-off. Static RAM holds data in flip-flops; dynamic RAM stores it as charge and must be refreshed.
- The ROM family is non-volatile: ROM is masked at manufacture, PROM is one-time programmable, EPROM is erased by ultraviolet light, EEPROM and Flash are erased and rewritten electrically — which is what makes on-aircraft data loading possible.
- Software is loaded and configuration-controlled; the aircraft data loader writes to non-volatile memory so the loaded part number survives a power cycle.
- ⚠ Exam trap: "volatile" refers to loss of data at power-off, not to how quickly it can be changed. EEPROM is electrically erasable but still non-volatile.
- Addressable locations
- locations = 2ⁿ for n address lines
- Bus directions
- address = unidirectional · data = bidirectional · control = mixed
- Byte multiples
- 1 byte = 8 bits · 1 kB = 1024 bytes
A processor has a 16-bit address bus and an 8-bit data bus. How much memory can it address, and in what size chunks?
2¹⁶ = 65 536 locations. With an 8-bit data bus each location holds one byte, so the addressable memory is 64 kB, transferred one byte at a time.
A fault report says an LRU "lost its configuration after a power interruption". Which memory type is implicated?
The configuration was being held in volatile memory (RAM) instead of a non-volatile device such as EEPROM or Flash — either a battery/keep-alive supply has failed or the write to non-volatile memory did not complete.
The fetch–decode–execute cycle
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Computer structure concept map
FreeBasic Computer Structure
Basic computer structure quiz
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